1. Field of the Invention
The invention relates to a method for manufacturing semiconductor memory devices and, more particularly, to a method for manufacturing semiconductor memory devices which each store therein information utilizing a capacitive element having an HSG (Hemispherical Grain) structure.
2. Description of the Related Art
Semiconductor memory devices (memories) are roughly classified into DRAMs (Dynamic Random Access Memories) and SRAMs (Static Random Access Memories), most of which are comprised of MOS (Metal Oxide Semiconductor) transistors excellent in integration density. Further, a DRAM can enjoy the above-mentioned advantage of high integration density more than an SRAM, to lower costs, thus finding a wide application field of various memory apparatuses including information equipment.
Also, since the DRAM utilizes capacitive elements to store information based on existence/nonexistence of charge in each of capacitive elements, it is necessary to limit a resultantly large area due to increasing integration density which area is occupied by these capacitive elements on its semiconductor substrate; with this, to compensate for a resultant decrease in capacitance of each capacitive element, various techniques have been worked out in terms of structure of the capacitive elements.
With this, the DRAM includes a switching transistor (memory-cell selecting transistor) consisting of the above-mentioned MOS transistor for controlling inputting/outputting of information to its capacitive elements, in such a configuration that that memory-cell selecting transistor and one such capacitive element may make up a one-bit memory cell. Each capacitive element is connected to either a source of a drain of the MOS transistor of each memory-cell selecting transistor, so that information read/write operations are performed to the capacitive element when a word-line signal is applied to a gate electrode of that MOS transistor to turn it ON or OFF.
Since the capacitive elements are reduced in size with improvements in integration density and fine patterning of DRAMs, an appropriate method must be developed to increase the capacitance of each of the capacitive elements. In an attempt to do so, one method is provided for increasing surface area of capacitive insulator film of each capacitive element. Another method is provided for reducing film thickness of the capacitive insulator film. Conventionally, the above-mentioned HSG technology has been employed. This HSG technology attempts to form an HSG on a surface of a lower electrode of each capacitive element, to thereby increase the surface area of the capacitive insulator film.
As shown in FIG. 14, for example, on a P-type silicon substrate 51 of a DRAM, N-type source region 52 and N-type drain region 53, a gate insulator film 54, and a gate electrode 55 are formed in a region isolated by an element-isolating insulator film 57, thus forming an N-type MOS transistor 56 as the memory-cell selecting transistor. The gate electrode 55 here is connected to a word line and a source electrode (not shown), to a bit line. Also, so as to cover a whole surface, a first inter-layer insulator film 58 and a second inter-layer insulator film 62 are formed, in such a configuration that the first inter-layer insulator film 58 has a first contact hole 59 formed therein, in which first contact hole 59 is so formed a contact plug 60 as to be connected to the N-type drain region 53 and also the second inter-layer insulator film 62 has a second contact hole 63 formed therein, in which second contact hole 63 is so formed a capacitive element 70 as to be connected to the contact plug 60.
Thus, the capacitive element 70 is provided with a lower electrode 71, a capacitive insulator film 72, and an upper electrode 73. The lower electrode 71 has an HSG 74 formed by HSG technology thereon. Also, the lower electrode 71 has an impurity diffused therein to prevent lowering of its capacitance due to its own depletion and has a barrier film 75 formed thereon to prevent the impurity from being diffused to outside.
With this, after the capacitive insulator film 72 is formed on the barrier film 75, this capacitive element 70 needs to undergo oxidation processing (annealing) to suppress a leakage current and an initial failure rate caused by being a capacitive element. Conventionally, this oxidation has been performed using an FA (Furnace Anneal) processing at about 800xc2x0 C. which uses a diffusion furnace as its heating source.
Recently, on the other hand, with progress in the semiconductor processing technologies, a semiconductor device,such as a processor and a like, having a large-scale logic part and DRAM part mixed on a same semiconductor substrate has been developed. To improve the operation speed of such the semiconductor device, such a device region as constituting the logic part, in particular, needs to undergo a suicide process, so that the above-mentioned device requires for its manufacturing a lowered processing temperature, that is, so-called low-temperature processes.
The prior-art method for manufacturing the semiconductor device, however, suffers from the following problems.
A first problem is that although the capacitive element can be increased in capacitance by employing the HSG technology, its service life is degraded as compared to those manufactured without using the HSG technology. The reasons for this problem are described below with reference to FIGS. 12A and 12B.
As shown in FIG. 12A, when the lower electrode 71 has an HSG 71a formed thereon, this HSG 71a in turn has a sharp constriction 71b formed at its root. This remarkably damages coverage of the capacitive insulator film 72 formed above the lower electrode 71, thus reducing a film thickness T of a part of the capacitive insulator film 72 as shown enlarged in FIG. 12B which part is formed near that constriction 71b and its vicinity portion A. Therefore, an electric field is concentrated during operation to the above-mentioned part of the capacitive insulator film 72 having a small film thickness T at the constriction 71b, to cause a leakage current to flow from that portion, thus degrading the service life of the capacitive element. Specifically, its service life is shortened by roughly one digit as compared to a capacitive element having no HSG formed thereon. With this, it needs to be improved so as to enjoy a service life almost equivalent to that of the capacitive element having no HSG formed thereon.
A second problem is that when the capacitive insulator film is decreased in film thickness to increase the capacitance of the capacitive element, larger thermal stress is applied which is generated by oxidation performed after that capacitive insulator film is formed, thus increasing occurrence of initial failure rates.
That is, as mentioned above, after the capacitive insulator film is formed, for example to reduce the leakage current and-the initial failure rate due to being a capacitive element, oxidation is required by use of, for example, the above-mentioned FA processing, in which case, however, influence of the thermal stress applied during this oxidation process cannot be avoided if processing temperature is high. To reduces this influence, the oxidation process must be performed at a lower temperature, but if the temperature is lowered too much, an essential object cannot achieved by the oxidation process. Therefore, the thermal stress must be suppressed to thereby reduce the initial failure rate.
FIG. 13 is plotted in terms of a TDDB (Time Dependent Dielectric Breakdown) property. As can be seen from the FIG.13, formation of the HSG degrades the service life and the reduction in a film thickness Teff (film thickness, calculated as oxide film thickness) of the capacitive insulator film further degrades the capacitive element.
A third problem is that processing for preventing depletion of a capacitive element, which is required by a temperature-lowering process, is effective for that purpose by diffusing the impurity employed but not in improvement of the service life.
That is, when the temperature-lowering process is performed, depletion due to a lowered temperature develops at the capacitive element, thus decreasing its capacitance. To prevent this effectively, after the lower electrode is formed, the capacitive element can undergo annealing in an atmosphere of a phosphine gas to diffuse phosphorus into the lower electrode, which is followed by light etching of the surface of the lower electrode. If, however, the insulator film and the upper electrode are formed afterward to complete the capacitive element, the influence due to the lowered temperature remains as is, thus unavoidably degrading the service life.
As mentioned above, the prior-art method for manufacturing the semiconductor memory device has the above-mentioned first through third problems and so cannot improve the service life of the capacitive element nor reduce the initial failure rate, thus finding it difficult to improve reliability of the capacitive element.
In view of the above, it is an object of the invention to provide a method for manufacturing semiconductor memory devices that can prolong service life and also reduce initial failure rate of a capacitive element having an HSG structure, thus improving reliability.
According to an aspect of the present invention, there is provided a method for manufacturing semiconductor memory devices by forming a memory-cell selecting transistor on a semiconductor substrate and then forming a capacitive element so as to be connected to one operating region of the memory-cell selecting transistor, including the steps of:
forming, as an inter-layer insulator-film forming process, the memory-cell selecting transistor on the semiconductor substrate and then forming an inter-layer insulator film on the semiconductor substrate;
forming, as a lower-electrode forming process, a contact hole in the inter-layer insulator film and then forming a lower electrode of the capacitive element so as to be connected to one operating region of the memory-cell selecting transistor;
forming, as a capacitive-insulator-film forming process, a capacitive insulator film of the capacitive element above the lower electrode;
oxidizing, as an oxidation process, the semi-conductor substrate in a furnace at a temperature of 700-780xc2x0 C. for a time of 30-50 minutes; and
forming, as an upper-electrode forming process, an upper electrode of the capacitive element above the capacitive insulator film.
In the foregoing, a preferable mode is one wherein the lower-electrode forming process includes the steps of: forming, as a first step, a first amorphous silicon film in the contact hole in the inter-layer insulator film; forming, as a second step, a second amorphous silicon film containing microcrystal above the first amorphous silicon film, to form an HSG by using as a nucleus the microcrystal contained in the second amorphous silicon film; diffusing, as a third step, an impurity into an HSGl; and removing, as a fourth step, a surface layer of the HSG.
Also, a preferable mode is one wherein the lower-electrode forming process includes the steps of: forming, as a first step, a first amorphous silicon film in the contact hole in the inter-layer insulator film; forming, as a second step, a second amorphous silicon film containing microcrystal on a surface of the first amorphous silicon film, to form the HSG by using as the nucleus the microcrystal contained in the second amorphous silicon film; and removing, following the second step, a surface layer of the HSG as a third step.
Also, a preferable mode is one wherein by the third step, the phosphine (PH3) gas is introduced into the reactive apparatus to perform annealing at a temperature of 500-780xc2x0 C. at a pressure of 5-400 Torr, thus diffusing phosphorus into the HSG.
Also, a preferable mode is one wherein by the third step, a phosphine gas is introduced into a reactive apparatus to start diffusion of phosphorus into the HSG in order to perform annealing for a predetermined time, and then, with the introduction of the phosphine gas as continued, the temperature of the annealing is lowered.
Also, a preferable mode is one wherein the fourth step is followed by a fifth step of removing a chemical oxide film formed on the HSG surface.
Furthermore, a preferable mode is one wherein the fifth step involves processing by use of an etchant having a selection ratio between a material of the HSG or the lower electrode and the chemical oxide film.
With the above aspect, after the HSG is formed, its surface layer can be removed to round off a shape of the HSG constriction, thus suppressing concentration of an electric field for improvements in the service life and depletion. Also, after the HSG is formed, an impurity can be diffused to improve the service life and the depletion. Also, after the capacitive insulator film is formed, the oxidation processing can be performed in a wet oxidation atmosphere inside the furnace at a relatively low temperature for a relatively long time, to relax thermal stress on the capacitive insulator film, thus reducing the initial failure rate.
Accordingly, reliability of the capacitive element having an HSG structure can be improved by prolonging its service life and reducing its initial failure rate.